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Honored Contributor
Honored ContributorDDR2 controller of ALTMEMPHY problem
first,i am sorry about my english...==! fpga:Cyclone IV E EP4C40F23C8 ddr2:MT47H32M16-25E.Data bitwidth is 16.There are 4 chips,two of them connect to the bottom side of FPGA,another two is c...
Altera_ForumHonored Contributor
Honored Contributorhttps://dl.dropbox.com/s/q8v3ic4oss7v2fx/ddr2_ctrl5.jpg
https://dl.dropbox.com/s/seqhnhokst0r1vb/ddr2_ctrl6.jpg https://dl.dropbox.com/s/ocjqiqdm2fvi8bo/ddr2_ctrl7.jpg https://dl.dropbox.com/s/43iojeu7b1tpgsh/ddr2_ctrl8.jpg 3,after Instantiate ddr2 controller,i add xxx_example_top.v and xxx_example_driver.v to my project,and set the xxx_example_top.v as the top entry.. 4,run the ddr2_ctrl_phy_ddr_pins.tcl,ddr2_ctrl_phy_ddr_timing.tcl,ddr2_ctrl_pin_assignments.tcl,ddr2_ctrl_phy_report_timing.tcl, ddr2_ctrl_phy_autodetectedpins.tcl,ddr2_ctrl_phy_report_timing_core.tcl 5,pin assignment :run the pin_assignment_ddr2.tcl(see attchment) 6,timing contrain..add ddr2_ctrl_phy_ddr_timing.sdc and ddr2_ctrl_example_top.sdc... 7,start analysis & Synthesis.... 8,create signaltap instance and add the local_init_done signal.. 9,full compile...
