Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

DDR2 controller of ALTMEMPHY problem

first,i am sorry about my english...==!

fpga:Cyclone IV E EP4C40F23C8

ddr2:MT47H32M16-25E.Data bitwidth is 16.There are 4 chips,two of them connect to the bottom side of FPGA,another two is connect to the top side of FPGA,see the attchment sch_ddr2.pdf for detail.

software:Quartus II 13.1

attachment 2 is the tcl script of pin assignment .

the ddr2 controller's reference clock source is a a 50MHZ crystal (PIN_G1)

my flow of create a ddr2 test project:

1,create a empty project for EP4C40F23C8

2,Instantiate a ddr2 controller of ALTMEMPHY controller,and config...as the picture show

https://dl.dropbox.com/s/mq1t8gc7c3m2rv1/ddr2_ctrl1.jpg

https://dl.dropbox.com/s/iqdon8fp37a15fs/ddr2_ctrl2.jpg

https://dl.dropbox.com/s/l5cssglf0enc0ac/ddr2_ctrl3.jpg

https://dl.dropbox.com/s/rril6uyyst2ptcq/ddr2_ctrl4.jpg

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    https://dl.dropbox.com/s/q8v3ic4oss7v2fx/ddr2_ctrl5.jpg

    https://dl.dropbox.com/s/seqhnhokst0r1vb/ddr2_ctrl6.jpg

    https://dl.dropbox.com/s/ocjqiqdm2fvi8bo/ddr2_ctrl7.jpg

    https://dl.dropbox.com/s/43iojeu7b1tpgsh/ddr2_ctrl8.jpg

    3,after Instantiate ddr2 controller,i add xxx_example_top.v and xxx_example_driver.v to my project,and set the xxx_example_top.v as the top entry..

    4,run the ddr2_ctrl_phy_ddr_pins.tcl,ddr2_ctrl_phy_ddr_timing.tcl,ddr2_ctrl_pin_assignments.tcl,ddr2_ctrl_phy_report_timing.tcl,

    ddr2_ctrl_phy_autodetectedpins.tcl,ddr2_ctrl_phy_report_timing_core.tcl

    5,pin assignment :run the pin_assignment_ddr2.tcl(see attchment)

    6,timing contrain..add ddr2_ctrl_phy_ddr_timing.sdc and ddr2_ctrl_example_top.sdc...

    7,start analysis & Synthesis....

    8,create signaltap instance and add the local_init_done signal..

    9,full compile...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    https://dl.dropbox.com/s/u55onq23etlxywi/report1.jpg

    problem:

    1,the signal of local_init_done is always low when the i set the reference clock of ddr2 controller to 50MHZ,I use a Oscilloscope to test pin A-DDR2-CK,it is 125MHZ

    2,the signal of local_init_done is high when i set the reference clock of ddr2 controller to 100MHZ(actually is a 50MHZ crystal.............),I use a Oscilloscope to test pin A-DDR2-CK,it is 62.5MHZ(==！.................................)

    https://dl.dropbox.com/s/ewa48imv4ae6zda/report2.jpg

    question:

    1,how to use altpll's clk output as the input refence clock of ddr2 controller,because i must Instantiate two controller.I have tried to add a altpll,but some critical warning turn out about dedicated clock.....

    2,after i add the mem_addr siganl to signaltap instance,there are many critical warning...more then 200....

    if you can't see the picture please download the attachment 3:screenshot.zip