Honored Contributor
Honored ContributorHi,
The CIII dev kit has a total of 72 bits wide DDR2 memory (split between the top and bottom banks as 32 bits and 48 bits), so if you use both banks simultaneously (and I am not sure whether you can do this with a single HPC DDR2 controller) then you have 72*400 = 28gbps bandwidth. Remember that with the frame buffer you have a reading and writing port, so to sustain 1080p60 through the frame buffer you need twice the bandwidth of the video stream. 1920 * 1080 * 60 * 24 * 2 = about 6gbps. Which is still much less than what you have available, so it seems easy. You also need to have a system clock in excess of 125MHz to be able to sustain the data transfers of the Avalon ST interfaces (1920*1080*60=124.4M). If you run the DDR2 at 200MHz, then this would be s logical choice of system clock, but in my experience, on a CIII, this is not that easy to achieve and for any realistic system (not just a demo), you end up with a system clock of 90, maybe 100MHz. Although it is possible to get a 1080p60 stream through a CIII, it is not easy and you would probably need a fast speed grade device (also note that 200MHz DDR2 is only possible on the fastest speed grade device. On the normal speed grade -8 device, you are limited to 166MHz). Regards, Niki
