DDR (Source Synchronous O/P) Interface - unconstrained clock?

Hi,

I've been working on a DDR interface between two cards across a backplane and followed the advice offerred by Altera AN33. I have constrained my outputs relative to the output clock (from a PLL). TimeQuest is happly with the timing and it seems to do what I want, but it reports the output clock as unconstrained. Should I apply a constraint or exception to this? I don't think it is absolutely necessary because the output data is constrained wrt to the output clock but I would like to clear the unconstrained path message for completeness.

Regards,

Dave.

My SDC is as follows:

create_clock -period 40.000 -name CLK_25 CLK_25

create_clock -period 10.000 -name VIRTUAL_RX_SOURCE_CLK

create_clock -period 10.000 -name RX_CLK -waveform {3.125 8.125} LVDS_RXC_LINK0_

derive_pll_clocks

create_generated_clock -name TX_CLK -source {inst2|altpll_component|auto_generated|clk[3]} {LVDS_TXC_LINK0_}

set_clock_groups

-exclusive

-group

{

CLK_25

}

-group

{

inst2|altpll_component|auto_generated|pll1|clk[0]

inst2|altpll_component|auto_generated|pll1|clk[3]

TX_CLK

}

-group

{

inst2|altpll_component|auto_generated|pll1|clk[1]

}

-group

{

RX_CLK

}

# DDR Output timing

set_output_delay -clock {TX_CLK} -max 1.51 [get_ports LVDS_TXD*]

set_output_delay -clock {TX_CLK} -max 1.52 [get_ports LVDS_TXD*] -add_delay -clock_fall

set_output_delay -clock {TX_CLK} -min -1.53 [get_ports LVDS_TXD*] -add_delay

set_output_delay -clock {TX_CLK} -min -1.54 [get_ports LVDS_TXD*] -add_delay -clock_fall

set_output_delay -clock {TX_CLK} -max 1.55 [get_ports LVDS_TXE*]

set_output_delay -clock {TX_CLK} -max 1.56 [get_ports LVDS_TXE*] -add_delay -clock_fall

set_output_delay -clock {TX_CLK} -min -1.57 [get_ports LVDS_TXE*] -add_delay

set_output_delay -clock {TX_CLK} -min -1.58 [get_ports LVDS_TXE*] -add_delay -clock_fall

set_false_path -setup -rise_from {inst2|altpll_component|auto_generated|pll1|clk[0]} -fall_to {TX_CLK}

set_false_path -setup -fall_from {inst2|altpll_component|auto_generated|pll1|clk[0]} -rise_to {TX_CLK}

set_false_path -hold -rise_from {inst2|altpll_component|auto_generated|pll1|clk[0]} -rise_to {TX_CLK}

set_false_path -hold -fall_from {inst2|altpll_component|auto_generated|pll1|clk[0]} -fall_to {TX_CLK}