DDR (Source Synchronous O/P) Interface - unconstrained clock?

Good job setting this up. Source synchronous double-data rate is not trivial to do. As for the output clock being "unconstrained", that is correct and only because you're not constraining it "as data". Personally I've never seen anyone do this, and have just lived with the error. You could probably put a set_max_delay 20.0, set_min_delay 0.0, and that would constrain it and should make the error go away, but my feeling is that it's an extra constraint that doesn't really reflect any requirements in your system.