DDR PIN placement error

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Is there a document that reveals the DQ/DQS/DM mysteries

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The Cyclone IV pinout files are here:

http://www.altera.com/literature/lit-dp.jsp?category=cyc%204&showspreadsheet=y

They list the DQS etc.

When comparing parts, I use the text version of these files and write Tcl scripts to parse the files.

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why they are fixed to these 'exact' locations ?

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DDR2/3 interfacing requires phase shifting the strobe clock to capture the data. Hence a DQS is grouped with a block of DQ registers.

Cheers,

Dave