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Altera_Forum
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18 years ago

DDR I/O with cyclone 3 devices, is it possible??

Hi

I am new to this forum and i am posting for the first time. I seek help with a design issue.

I have a MAX104 ADC i wish to use with a cyclone 3 device. I already know how to interface it with xilinx vertix 2 pro device that provides a DDR I/O facility.

I am using the ADC's(clocked at 1Ghz) mux feature to allow a data output rate of 500Mhz and further using the DDR method achieve an effective 250Mhz.

I have goen through the datasheet of lattice ECP2 device which also discusses about using the I/O in a DDR2 configuration.

Can someone please guide me on whther cyclone 3 supports DDR I/O or i am missing out some information.

Thank You

Rohit

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    For the input direction, Cyclone III implements DDR registers in LEs, not in the I/O cells. In the device handbook, see "DDR Input Registers" under "Cyclone III Memory Interfaces Features" in Volume 1, Section II, Chapter 9.

    You can use the altddio_in megafunction. Even though the input registers are actually in LEs, designing with the megafunction is similar to using I/O cell DDR input registers in other device families. The megafunction will let the Fitter know to place the registers near the device pins. You should get messages like these:

    --- Quote Start ---

    Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing

    Info: Node "altddio_in:altddio_in_component|ddio_in_s3e:auto_generated|input_cell_h[0]" is constrained to location LAB_X1_Y1_N0 to improve DDIO timing

    Info: Node "altddio_in:altddio_in_component|ddio_in_s3e:auto_generated|input_cell_l[0]" is constrained to location LAB_X1_Y1_N0 to improve DDIO timing

    --- Quote End ---