DDR I/O with cyclone 3 devices, is it possible??

For the input direction, Cyclone III implements DDR registers in LEs, not in the I/O cells. In the device handbook, see "DDR Input Registers" under "Cyclone III Memory Interfaces Features" in Volume 1, Section II, Chapter 9.

You can use the altddio_in megafunction. Even though the input registers are actually in LEs, designing with the megafunction is similar to using I/O cell DDR input registers in other device families. The megafunction will let the Fitter know to place the registers near the device pins. You should get messages like these:

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Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing

Info: Node "altddio_in:altddio_in_component|ddio_in_s3e:auto_generated|input_cell_h[0]" is constrained to location LAB_X1_Y1_N0 to improve DDIO timing

Info: Node "altddio_in:altddio_in_component|ddio_in_s3e:auto_generated|input_cell_l[0]" is constrained to location LAB_X1_Y1_N0 to improve DDIO timing

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