Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

DDR Input Same Edge vs Opposite Edge transfer

Hi, Background 12 bit Serialized DDR data stream coming into the FPGA via LVDS at 960Mbps. 480MHz bitclock along with data channels being sent. 80Mhz frame clock too. I was wondering ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I needed to add all my design files along with the testbench file in the EDA Simulation settings. Not adding worked for rtl simulation. Not gate level.

I've simulated it and it seems to be working according to my eye..

Thanks

ZubairLK