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Hi,
Background
12 bit Serialized DDR data stream coming into the FPGA via LVDS at 960Mbps. 480MHz bitclock along with data channels being sent.
80Mhz frame clock too.
I was wondering if it matters in a long data stream if we constrain the design on same edge transfer vs opposite edge transfer.
If it is wrong, the first and last sample will be long. But in a continuous stream it shouldn't matter? Should it?
Opposite edge transfer is better for timing constraints and eases timing.
I can't seem to figure a way to simulate it. Can't get gate level simulations to run on Model Sim and verilog is functionally the same..
Comments and feedback welcome.
Thanks
Zubair
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My understanding is that the data stream once it arrives for latch it does not matter which edge captures first since there is no memory of how or from which edge data was launched. The important thing is to realise that the default settings are too restrictive and need be relaxed across edges and it then depends on the following possibilities:
No PLL, or PLL set to 0 or < 0 => edge aligned input defaults
PLL set to > 0 => centre aligned input defaults.
User can then choose settings for either:
Same edge capture
Opposite edge capture
thus there will be four sets of possibilities:
Edge aligned input, same edge capture
Edge aligned input, opposite edge capture
centre aligned input, same edge capture
centre aligned input, opposite edge capture
Exceptions(multicycle or false paths) vary accordingly.
edit:
The only issue that I see is if input offset values from rise edge differ from those of falling edge in which case the tool needs to identify the two separately and apply worst case.
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