DDR controller pin placement

Hi All,

I have two problems with the 16 bit DDR controller generated by Megawizard in my design with EP3C16E144I7.

(1) I assign CK to pin 71 and CK# to pin 72. After compilation, I get the following warning:

Warning: CK/CKn pin DDR_CK_P has been placed on a PLL CLKOUT pin. They should be placed on Differential IO (DIFFIO) pins only.

Warning: CK/CKn pin DDR_CK_N has been placed on a PLL CLKOUT pin. They should be placed on Differential IO (DIFFIO) pins only.

I check the pinout table of my Cyclone III device, and find pin 86,87 are DIFFIO pins as suggested by the warning message.

But after I assign CK and CK# to these two new pin locations, the fitter fails. Now I get errors:

Error: Cannot place I/O pin mem_clk[0] in pin location 87 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available

Error: Cannot place I/O pin mem_clk_n[0] in pin location 86 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available

It seems the hint given by the warning message is not on the right road. Shall I just ignore these two warnings and stick to the original pin assignment?

By the way, I am using Quartus 9.1sp1, could it be a bug in this old version?

(2) in the generated XXX_example_top.vhd, CKE, CK/CK# and nCS are all declared as std_logic_vector(0 downto 0), while in my top-level design, they are declared as std_logic. So when I instantiate XXX_example_top in the top-level, I can't connect these pins directly to the top-level ports, otherwise I get VHDL syntax error. I have to manually change these pins to std_logic in XXX_example_top.

Is there a workaround to this?

Thank you in advance for any advice!