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Altera_Forum
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14 years ago

DDR controller pin placement

Hi All, I have two problems with the 16 bit DDR controller generated by Megawizard in my design with EP3C16E144I7. (1) I assign CK to pin 71 and CK# to pin 72. After compilation, I get ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yeah, I think that is something I can expect, because this is just a warning.

What I don't understand is : if I really change CK/CK# to DIFFIO pins, why do I get an error, which is even worse? Does this mean the warning message is quite misleading?

BTW, zju2010, do you also have the VHDL data type std_logic_vector(0 downto 0) in your generated DDR controller? Can you make it generate std_logic, instead of std_logic_vector(0 downto 0)?