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Altera_Forum
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9 years ago

ddr bi-directional with different input/output clocks

Greetings, I am wondering what the correct megafunctions/primitives are for implementing input/output dual-data-rate data lines for a DDR memory device. I'm on a Cyclone IV. Here are my require...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

I think there is no data in dataout_l because on this path there is aditional latch which is enabled from inclock high level. So in your case data at falling edge of inclock is registered but not passed trough latch. Give it another inclock pulse and you will see data on dataout_l port. If you read ALTDDIO_BIDIR IP Core user guide you will found out how ALTDDIO_BIDIR is implemented in device and timing waveforms.

Regards