dcfifo timing details

I've actually never seen that request before, but can see how it would help your application(and someone else chimed in they've seen this). I'll see what I can do to get someone to look at it. My concern is that, in your application, I don't think what you have would meet timing anyway. Note that "write_ptr_synced_in_rdclk" is a gray coded value. You can't do simple math with a gray code(at least carry-chain math), so you need to either convert it back to binary or go through a large decode just to do that first line. So even if it were made to work in 1 clock(and at first glance it looks all right, but I haven't really dissected it) I doubt it would make timing.

To get a better idea of what's going on, go to the RTL viewer. The behaviour is pretty understandable. Note that the combinatorial output for rdusedwd is just a single adder, which should be able to use the carry chain. If that can't meet timing in your design, I What are your read and write clock frequencies? I'm trying to think of another way, and that might help.