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Altera_Forum
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17 years ago

DCFIFO read/write request control

Hi, I'm using dcfifo's in a design with the rdreq and wrreq signals. The clock on both sides of the fifo is the same frequency but it will be out of phase. When the fifo comes out of reset, sho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks Kaz.

I've been using signal tap to look at the fifo flags on both sides to see what's happening. I presume as soon as rdempty goes low (assuming when it's high, nothing has been written), I can start to read. From here on, I suppose I can keep the rdrq/wreq lines tied high?

I know when you build the fifo, there is an option that asks if you want to sync aclr to wrclk. I've kept this disabled becaue I use some regs to sync the reset to wrclk. With this option on, I had problems.