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YEAHHHH, EXCELLENT, I've just tried to put a CLKINT (which make the clock line global) and the problem disappears. I have had some problems which were solved by using a CLKINT before, but didn't know why it helped. Now turns out it's all about the clock skew problem.
Yeah, it is a correlator that I'm designing, I tried 2 methods, the other was to use a series of Shift register and Multipliers, but no way it's fit in the chip I was given. The MAC method involves so many problems, it's a nightmare.
Could you think of any other methods?
J.
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Glad to help!
Whilst I have designed a number of correlators ours always have to run flat out so we sacrifice resources to get speed (and use quite large FPGAs). The current one has 140 parallel accumulators and recirculates the complex PN sequence in a 2bit wide 80 bit long shift register (rather than circulating the 24 bit wide data). I've also implemented the same correlator as a Matched Data Filter arrangement - they take more or less the same resources.
In your case you could maybe reduce the resource usage by changing from using a shift register to using a Circular buffer which would more easily map into a RAM (assuming your Actel has RAMs). The VHDL would be a little bit more complex but the synthesised logic would be much smaller.
Mark.
Honored Contributor
