Data corrupted, any problem with VHDL codes

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Normally I would agree, but if you look at his doc5 (granted not that easy as it RARed) you'll see that clk_in and clk_out are related and mutually exclusive - basically he is clocking in data to a bloody great shift register - then reading out the whole shift register (for some reason) and then clocking in another word. So metastability wise it shouldn't be an issue but as my previous post mentions he has a clock skew/timing issue one one wire!

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Thanks Mark, yeah, as you said, the CLK_IN and CLK_OUT are related to each other, 66 CLK_OUT pulses are covered by 1 CLK_OUT, (in my test, the Clocks were controlled by a microprocessor).

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Well you can see by the way the error propogates through to subsequent addresses that the error occurs at the input phase (in the shift register) and it is bit 5 (16) that is causing problems - to me it looks like your enormous shift register has a timing problem (posibly due to clock skew) on this one bit between those two elements.

Do you get any timing warning from the compiler? Did you use the proper global clock lines for the CLK_IN to keep skew to a minimum? Have you defined any timing constraints?

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Yeah, I think the problem arised at the input phase, which consists of writing the data into content(words - 1) and a series of shifting process. But if you plot a graph of the last column (where the data was first written in --> fine), you will see it is likely the shifting process that cause the error.

I don't have any timing warning from the compiler and no global clock lines for the CLK_IN has been used yet (will give it a go)... and no time constraints was defined...

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So looks like a redesign is the only way to go!

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Thanks vernmid for your suggestion, actually, I'm designing a hardware correlator using a MAC circuit. Wish I could change the design, however the circuit was a given and the FPGA chip doesn't have enough resource for me to drive the design to other directions.

Thanks everyone, for your contribution.