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There is a chance, but as the other people have said, if the in_clock and out_clock are unrelated then this design will now work whatever the technology used.
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Normally I would agree, but if you look at his doc5 (granted not that easy as it RARed) you'll see that clk_in and clk_out are related and mutually exclusive - basically he is clocking in data to a bloody great shift register - then reading out the whole shift register (for some reason) and then clocking in another word. So metastability wise it shouldn't be an issue but as my previous post mentions he has a clock skew/timing issue one one wire!
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