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Actually, I used an Actel FPGA (which I don't like but company does) for this design, not Altera. Is there any chances the way the the logic elements and the net were placed and routed inside the chip corrupted the data?
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There is a chance, but as the other people have said, if the in_clock and out_clock are unrelated then this design will now work whatever the technology used.
Imagine the Content(0) word. Due to difference in routing delays for each bit, each bit will change at a slightly different delay after input clock rises.
Now imagine you try and latch the output using output clock. Depending on the relationship of the input and output clock edges at this instant it is possible that you will see some of the bits in the word as the new value and some as the previous value. Hence corrupt data!
This comment ignores the crucial but unpleasant effects of metastability whereby you violate setup/hold times of flip-flops by changing the input data using a different clock to that latching the data. Also causing corrupt data.
So looks like a redesign is the only way to go!
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