Data corrupted, any problem with VHDL codes

Well you can see by the way the error propogates through to subsequent addresses that the error occurs at the input phase (in the shift register) and it is bit 5 (16) that is causing problems - to me it looks like your enormous shift register has a timing problem (posibly due to clock skew) on this one bit between those two elements.

Do you get any timing warning from the compiler? Did you use the proper global clock lines for the CLK_IN to keep skew to a minimum? Have you defined any timing constraints?

Your spreadsheet and your doc6 do not seem to match up by the way.One shows the error occuring between elements 57 and 56 of the shift register whilst doc6 implies it is elements 63 and 62.

Mark.