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Altera_Forum's avatar
Altera_Forum
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17 years ago

Data corrupted, any problem with VHDL codes

HI everyone. I just have a quick question to ask. When we use the LOOP in VHDL, is there any chances that the number of times the LOOP is repeated affects the data, say, in the following pie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thank you for having a look at my post.

Following is the link to some illustration for my design.

datacorrupted.rar (http://www.filefactory.com/file/a01448d/n/datacorrupted_rar) (scroll down to option2, click on the link Download With FileFactory Basic)

doc5.pdf is the clk_in and clk_out waveform.

doc6.pdf is how I want the output to be.

doc7.xls is the real data I captured (after transfering the output to a Microprocessor and have it printed on screen). As you can see, at column BF, some of the data is corrupted (one bit changes) making the waveform change dramatically (you can plot a graph of column BF and BE to see the difference).

Please note that the clocking was control externally by the microprocessor which is much simpler than internally.

The 99 points of data were stored in a FIFO

I could have used a built-in RAM (with 99 points stored from address 0 to 98) and ignore the VHDL RAM for this design, but doing this will result in a really complicated addressing system.

Any suggestion after having a look at the diagram and data would be really appreciated.

Thank you

J