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Altera_Forum's avatar
Altera_Forum
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15 years ago

Data between gated clk's

Hi, I have a design that needs to use gated clk's in order to reduce the power consumption. I try to avoid using any speciel cells or PLL's, because I'm going to port it to an ASIC later on - but ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you for your reply. I'm actually very glad you can see the purpose :) I thought I would be able to make the 2 clk's similar in time, but as I understand it changes the hold time for the data signals instead.

Thx again.