New Contributor
Frequent ContributorHi Zjef,
Have you enable the tx_std_elecidle?
When you enable this option, you will have an extra input port (tx_std_ elecidle). When this signal is asserted, it forces the transmitter to electrical idle. This signal is required for the PCI Express protocol and you need to control it.
For detailed info sharing resources. Please go through this.
Cyclone V Device Handbook: Volume 2: Transceivers
V-Series Transceiver PHY IP Core User Guide
Hope it will help you. Please feel free to ask any further question.
If still facing issue, please share your project and i will resolve the issue, if any at my end.
Thank you
Kshitij Goel
New ContributorHi K**bleep**ij,
Yes, the tx_std_elecidle port is enabled.
I have attached a minimal setup showing the issue.
The top level contains two Transceiver Native PHY Cyclone V instances. The first one has only the transmitter path enabled (PHY_TXonly), the second one both transmitter and receiver (PHY_TXRX).
Both have their tx_std_elecidle port controlled by a top level input port. However when you look in the technology map viewer, the idle input of the PHY_TXonly instance is synthesized away.
I have also included a Modelsim simulation that shows that the tx_std_elecidle input of PHY_TXonly has no effect, while the one of PHY_TXRX works as expected (simulation/modelsim/msim_setup.do should set up everything).
Thanks,
Zjef
Frequent ContributorHi Zjef,
When tx_std_elecidle [<n>-1:0](input) is asserted, it tries to enable a circuit to detect a downstream receiver. But you are not using any receiver for PHY_TX only. So, it is having no effect. And this signal must be driven low when not in use because it causes the TX PMA to enter electrical idle mode with the TX serial data signals in tristate mode. Enabling of this signal is required only for the PCI Express protocol.
Application of the tx_std_elecidle signals stops transmission of any TX data, but the output remains terminated to Vcm through the on chip TX termination to Vcm. The TX termination is typically 50R. And this is relatively low impedance, tristate would be high impedance.
The PCI Express specification defines “Electrical Idle” as “The state of the output driver in which both lines, D+ and D-, are driven to the DC common mode voltage.”
So the word “driven” also reinforces the belief that we don’t “tristate” the TX buffer. To tristate the TX buffer, we would need to switch off TX termination which we do not support dynamically.
Sure the Tx buffer is tristated but the termination remains in place.
You should be careful about the term “tristate” for the TX Pins in the userguide. This function was designed for PCI Express.
It is true that we tristate the buffer when asserting tx_std_elecidle(Native PHY) and tx_forceelecidle(Custom PHY). However, the TX Termination to Vcm remains in place, so there will still be a steady state voltage on the Tx pins. Depending on what you connect your transmitter to, this termination may create a potential divider.
The termination is typically 50R. This termination cannot be switched off.
Thank you
Kshitij Goel
