CycloneIII internal logic driving PLL

The Data/Strobe works like this: if the Data signal doesn't change state then the Strobe Signal changes state, therefore if you XOR them together you get a clock at 1/2 the data rate. This is a SMIA or Camera Link interface. My data rate is 96MHz and a I have a 48Mhz Osc going to the PLL. My recovered clock is the same frequency, so the dynamic phase shift should work. I haven't done this before so it should be interesting. I will connect a global clock output to a global clock input for Option B. Once this is working then I can use the AltLVDS_RX to deserialize the Data.:p