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Altera_Forum's avatar
Altera_Forum
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17 years ago

cyclone3 pll

hi while implementing the pll using mega function , it generated code with ENTITY pll IS PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thank you for all!

I found the solution:

I created a new library called "cycloneiii" exactly the name of the library he didn't access and edited its mapping to the one it should be.

By quitting and running again Gate Level simulation, I had my simulation.

Now I have another question :)

When running the Gate Level simulation, I found that two clocks doesn't have the same phase : there is a difference of some tens of picoseconds.

Is this difference from the pll or from modelsim?

Thanks