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Altera_Forum
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17 years ago

cyclone3 pll

hi while implementing the pll using mega function , it generated code with ENTITY pll IS PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ...
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Altera_Forum
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17 years ago

dear fvm

thanks for your reply...one doubt i have ask u is

i simulated that clock circuit(implemented by mega function).

but the generated output clock is coming only after some time, before that e no clock is coming, it showing as before simulation... file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-1.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-2.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-3.jpg file:///C:/Users/psg/AppData/Local/Temp/moz-screenshot-4.jpg