--- Quote Start ---
i gave the input inclk0 as 100 MHz, why it is giving IN STD_LOGIC := '0';
--- Quote End ---
There's no contradiction. Yes, you have to connect inclk0 to a 100 MHz input clock. But Quartus prefers to assign a default signal level, which take effect, if you don't connect a component's port pin. It doesn't make sense in this case, cause the MegaFunction can't operate in a meaningful way without connecting inclk0. But it's useful in many other cases, e.g. for an optional reset input. It's a general VHDL element, you may want to consult a text book for a detailed syntax description.
And yes, PLL operation can be simulated, e.g. by Quartus simulator.
Honored Contributor
