Honored ContributorDear Sir
If we use higher end CYCLONE 3 FPGA EP3C40FBGA780 as LVDS TRANSMITTER and lower end CYCLONE3 FPGA EP3C5144 as LVDS RECEIVER this combination will work out or not for lvds serialyzer and deserialyzer functionalty? CYCLONE 3 FPGA EP3C40FBGA780 works as master will tranmit data to more CYCLONE3 FPGA EP3C5144 devices in multi-drop mode thank you sir.
Honored ContributorYes it is possible to mix different Cyclones in this configuration. Have a look at page 7-9 of this document (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf) to see how to connect several Cyclone III in multidrop mode (called BLVDS by Altera).
I would suggest that you define all your inputs/outputs in two Quartus projects for both FPGAs, assign pins and do an I/O check before you route your board, just to be sure that your choice of pins and I/O standard is possible. When routing the board, pay special attention to the LVDS pair because any brutal change of impedance on the line will cause reflexions and degrade the signal. You must have stubs as short as possible between the LVDS pair and the FPGAs.Honored ContributorDear Sir
Thank u for reply How to interface between lvds tx/rx and altiobuf for blvdsHonored ContributorI'm sorry I don't understand your question. The link I gave you was about the connection of the LVDS pins outside the FPGA whereas altiobuf is an IP inside the FPGA.
Honored ContributorMultidrop as mentioned in your first post doesn't necessarily involve BLVDS. Do you also intend to transmit data from the slaves to the master? If so, as a half-duplex (two wire) or fullduplex (four wire) connection? How's the synchronization achieved? Synchronous with common clock or asynchronous (UART) transmission?
