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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cyclone3 fails to configure

Hi,

I have custom board with EP3C55F484. I'm trying to configure Cyclone

using .jic file in QuartusII 9.0. The problem is that after Quartus programmer says that "operation was successful" nothing happens. FPGA doesn’t configure itself.

In the message field I see:

Info: Started Programmer operation at Mon Sep 27 10:25:52 2010

Info: Configuring device index 1

Info: Device 1 contains JTAG ID code 0x020F50DD

Info: Configuration succeeded -- 1 device(s) configured

Info: Device 1 silicon ID is 0x14

Info: Erasing ASP configuration device(s)

Info: Programming device(s)

Info: Successfully performed operation(s)

Info: Ended Programmer operation at Mon Sep 27 10:26:02 2010

Several days ago everything worked fine but one sad morning it began to fail.

One more thing. Verification process fails too:

Info: Performing CRC verification on device(s)

Error: Verification failed for device number 1

Error: Operation failed

When I tried to use .sof file instead of .jic it all worked well. So it's

clear for me that my FPGA is not dead yet.

On oscilloscope I can see that:

- nConfig is always HIGH;

- Conf_Done is always LOW;

- nStatus is toggling with period ~120us;

- all AS signals (DCLK, ASDO,nCS and DATA) are OK, so I assume that FPGA is trying to configure but fails for some reason.

I’ve read this forum from top to bottom but didn’t find any solution.

Any helpful suggestions?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If the EPCS verification failes, you can't expect that the FPGA can be configured correctly with the EPCS data.

    I see a least these possible explanations:

    - the EPCS is defective (unlikely)

    - you managed somehow to protect a sector of the EPCS device (would be possible with the NIOS flash programmer or when you're operating a serial flash controller in your design)

    - the EPCS programming fails due to signal quality issues of the JTAG chain. This may be also caused by crosstalk of other signals (e.g. a clock) to the JTAG signals, particularly TCK.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    maybe a screen of your EPCS connection in the schematic would be helpfull!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    FvM, thank you for your quick reply.

    I created a simple project (with ALTASMI_PARALLEL megafunction) for Cyclone 3 to test my EPCS. Thus I was able to perform Read Status Operation and Read/Write Operations.

    In SignalTap Logic Analyzer I saw that status of EPCS was 0x00 and Read/Write operations were performed correctly.

    So, I think, it means that there are no protected sectors in my EPCS and signal quality issue of the JTAG chain is not the cause of my problem.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    OK, I replaced EPCS and now configuration and verification are successful. For some reason EPCS was defective, like FvM said.

    Does anybody know the reason why EPCS broke?