cyclone2, odd problems

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JTAG is one of those things that seems simple because it's such a low data rate

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You hit the point. Although the data rate is low, the FPGA internal logic processing TCK isn't. So you can achieve false JTAG clocking either by ringing edges or crosstalk from other on-board fast signals. The latter should be considered if configuration in a multiple devices chain fails, after ather parts of the design started operation.