cyclone2, odd problems

Just so I understand better ...

1 - What is the processor? Can you fully detail the JTAG chain (all components in the chain, the order of the components, any level converters?). My first suspicion is there is simply poor signal integrity in the JTAG chain circuitry. JTAG is one of those things that seems simple because it's such a low data rate, but it must be layed out correctly or it can provide no end of headaches. It will work some of the time and fail others. Engineers typically assume the JTAG chain is a no brainer only to suffer later on.

One of the best simple design guidelines is to route the clock in opposite direction of the data. So hit the last device in the chain with TCK first and procede to route TCK through all the devices in the chain in reverse order. Kind of like how you would route the clock to shift registers on a board.

2 - It would be extremely odd if the ROM itself were failing. I would consider that a last suspicion. Therefore, we ought to consider the surrounding circuitry instead.

a - Clocking. Is this a single clock ROM. Is the design meeting timing requirements? Is the logic that drives the address pins being driven by the same clock that's driving the ROM?

b - Reset. Is a proper reset being applied to the design?

c - Design. Is there anything in the design that might cause the wrong ROM address to be read after power-up.

Jake