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YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone10GX Temperature Issue

Hi,

I use a cyclone 10 gx fpga (10CX150YF780C5G) on my pcie card. One transceiver is used as a 10Gbps fiber link and other 4 transceivers are used as Gen1 Pcie X4 lanes. No external memory interface. The total power consumption is about 2W.

The problem is when fpga's die temperature rises above about 55C, the transceiver that is used to connect the fiber link(SFP) has occurred missing word error in transmitting side. I use the transceiver loopback function to monitor the data both at a remote receiver output and at the local loopback receiver output. They show exactly same fault. It tells us the PCS stage in the transmitter side has something wrong. The reference clock to the transceiver ATX-pll is 644.53125MHz. Other functions in the fpga is working well.

When I lower the temperature by add a fan to blow it, it works normally. Is there any one knowing how to fix it?

Thanks a lot!

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  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    If the LL 10G MAC IP + PHY is working fine in various temperatures range, then it could be due to your custom logic/design timing is not optimize.


    • YYang79's avatar
      YYang79
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Just make it clear, after changing the fPLL to a IOPLL in my code according to the LL 10G MAC IP example design, this is the only change, we have got this temperature issue solved.

      My question is what is the difference between these two PLLs when put them into this application?

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    By right, both fPLL (core mode) can IOPLL can be used. However, the physical locations are different between both PLLs, so the routing difference may slightly impact the timing if the design is not optimized.


    Usually, this is recommended to use IOPLL if this can generate the expected frequency for the core logic, and preserve the fPLL for high-speed transceiver usage.


    • YYang79's avatar
      YYang79
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Thanks for having been going through this issue so long time with me!

      Appreciated!

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

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