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YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone10GX Temperature Issue

Hi, I use a cyclone 10 gx fpga (10CX150YF780C5G) on my pcie card. One transceiver is used as a 10Gbps fiber link and other 4 transceivers are used as Gen1 Pcie X4 lanes. No external memory interfa...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

By right, both fPLL (core mode) can IOPLL can be used. However, the physical locations are different between both PLLs, so the routing difference may slightly impact the timing if the design is not optimized.


Usually, this is recommended to use IOPLL if this can generate the expected frequency for the core logic, and preserve the fPLL for high-speed transceiver usage.


  • YYang79's avatar
    YYang79
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Thanks for having been going through this issue so long time with me!

    Appreciated!