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YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone10GX Temperature Issue

Hi, I use a cyclone 10 gx fpga (10CX150YF780C5G) on my pcie card. One transceiver is used as a 10Gbps fiber link and other 4 transceivers are used as Gen1 Pcie X4 lanes. No external memory interfa...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Since this problem can replicate with internal loopback, can you please change the pin assignment as below and determine if there is channel dependency?

set_location_assignment PIN_AF25 -to "SFP_RXD0(n)"

set_location_assignment PIN_AG27 -to "SFP_TXD0(n)"

set_location_assignment PIN_AF26 -to SFP_RXD0

set_location_assignment PIN_AG28 -to SFP_TXD0

Besides, please refer to the attached screenshot, add the interface signals of native PHY to signal tap, and then compare the "tx_parallel_data" and "rx_parallel_data" to determine if there is a mismatch. The data drop may happen before this module.

  • YYang79's avatar
    YYang79
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    We always test the data at these points. We usually call them xgmii interface. Only difference is a logical conversion of words from big endian to little endian between Native PYH parallel and xgmii. The data at xgmii shows OK.

    I will add "tx_parallel_data" and "rx_parallel_data" into my signaltap to see if there is any difference.