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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone V Triple Speed Ethernet in Quartus 13.1

Hi

I'm Working with the Development Kit c5efa7.

I used the example board update portal and compiled it for myself in quartus 12.1 with the eclipse nios example Simple Socket Server (RGMII) everything worked fine. I could even connect the the included telnet server.

After that I tried to updae to 13.1 and the errors started....

First I realized quartus can't update the tse to 13.1 by itself.... so I had to do it manually.

After setting all settings exactly like they were and renaming the tse to "tse_mac" (which is essentially) I can at least compile everithing.

The hello world is working but the Simple Socket Server (RGMII) doesn't get an IP-Address.

I think the problem could be the connection of the tse in the top level of my design. I have now much more in/outputs than in 12.1

How do I connect my remaining in/outputs?

in 12.1:

.ena_10_from_the_tse_mac (ena_10_from_the_tse_mac),

.eth_mode_from_the_tse_mac (eth_mode_from_the_tse_mac),

.mdc_from_the_tse_mac (enet_mdc),

.mdio_in_to_the_tse_mac (enet_mdio),

.mdio_oen_from_the_tse_mac (mdio_oen_from_the_tse_mac),

.mdio_out_from_the_tse_mac (mdio_out_from_the_tse_mac),

.rgmii_in_to_the_tse_mac (enet_rx_d),

.rgmii_out_from_the_tse_mac (enet_tx_d),

.rx_clk_to_the_tse_mac (enet_rx_clk),

.rx_control_to_the_tse_mac (enet_rx_dv),

.set_1000_to_the_tse_mac (),

.set_10_to_the_tse_mac (),

.tx_clk_to_the_tse_mac (tx_clk_to_the_tse_mac),

.tx_control_from_the_tse_mac (enet_tx_en)

in 13.1

.tse_mac_mac_status_connection_set_10 ( ), // tse_mac_mac_status_connection.set_10

.tse_mac_mac_status_connection_set_1000 ( ), // .set_1000

.tse_mac_mac_status_connection_eth_mode (eth_mode_from_the_tse_mac), // .eth_mode

.tse_mac_mac_status_connection_ena_10 ( ), // .ena_10

.tse_mac_mac_rgmii_connection_rgmii_in (enet_rx_d), // tse_mac_mac_rgmii_connection.rgmii_in

.tse_mac_mac_rgmii_connection_rgmii_out (enet_tx_d), // .rgmii_out

.tse_mac_mac_rgmii_connection_rx_control (enet_rx_dv), // .rx_control

.tse_mac_mac_rgmii_connection_tx_control (enet_tx_en), // .tx_control

.tse_mac_transmit_clock_connection_clk (tx_clk_to_the_tse_mac), // tse_mac_transmit_clock_connection.clk

.tse_mac_receive_clock_connection_clk (enet_rx_clk), // tse_mac_receive_clock_connection.clk

.tse_mac_mac_mdio_connection_mdc (enet_mdc), // tse_mac_mac_mdio_connection.mdc

.tse_mac_mac_mdio_connection_mdio_in (enet_mdio), // .mdio_in

.tse_mac_mac_mdio_connection_mdio_out (mdio_out_from_the_tse_mac), // .mdio_out

.tse_mac_mac_mdio_connection_mdio_oen (mdio_oen_from_the_tse_mac), // .mdio_oen

.tse_mac_pcs_mac_rx_clock_connection_clk (enet_rx_clk), // tse_mac_pcs_mac_rx_clock_connection.clk

.tse_mac_pcs_mac_tx_clock_connection_clk (tx_clk_to_the_tse_mac), // tse_mac_pcs_mac_tx_clock_connection.clk

.tse_mac_mac_misc_connection_xon_gen ( ), // tse_mac_mac_misc_connection.xon_gen

.tse_mac_mac_misc_connection_xoff_gen ( ), // .xoff_gen

.tse_mac_mac_misc_connection_ff_tx_crc_fwd ( ), // .ff_tx_crc_fwd

.tse_mac_mac_misc_connection_ff_tx_septy ( ), // .ff_tx_septy

.tse_mac_mac_misc_connection_tx_ff_uflow ( ), // .tx_ff_uflow

.tse_mac_mac_misc_connection_ff_tx_a_full ( ), // .ff_tx_a_full

.tse_mac_mac_misc_connection_ff_tx_a_empty ( ), // .ff_tx_a_empty

.tse_mac_mac_misc_connection_rx_err_stat ( ), // .rx_err_stat

.tse_mac_mac_misc_connection_rx_frm_type ( ), // .rx_frm_type

.tse_mac_mac_misc_connection_ff_rx_dsav ( ), // .ff_rx_dsav

.tse_mac_mac_misc_connection_ff_rx_a_full ( ), // .ff_rx_a_full

.tse_mac_mac_misc_connection_ff_rx_a_empty ( ) // .ff_rx_a_empty

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Did you also update/rebuild the project BSP folder? The header files have to be refreshed and recompiled.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes, I did create new Projects (BSP and APP) after generatin in QSYS and compiling in Quartus.

    Does anybody know if the ffs have to be connected to any point?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Is there any tutorial available on how to upgrade the TSE IP core? I'm in the same situation that I want to switch from an older Quartus version (11.1) to 13.1 (last version which supports Cyclone III).

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi,

    I have the same problem, my triple speed ethernet is ok with previous version of TSE + FreeRTOS and LWIP but with the update not, i have sgdma tx and rx. The sgdma RX seem to receive data, tx can send data, but there a stop in TSE (i suspect something with the PHY i use marvel rgmii 88E1111). the TSE User guide don't talk about a major update, and i can't found what's change...

    Can someone has already get a Triple speed ethernet since quartus 13.1 ?? maybe could we see a .qsys file and vhdl example ???

    thanks

    Simon
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi guys. I'm a step back from all you in my studies about Cyclone V GX.

    For now I'm trying to do simple things like put GX transceiver in loopback mode to transmit and receive one packet (not ethernet fow now, any bit stream...).

    Can you guys guide me what is the best way to do this? Altera docs are nice but I'm still a bit confused... thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Please open a dedicated thread for your problem.

    Can someone give use help for the TSE quartus 13.1 problem ?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Simon,

    Were you able to get you issue resolved? I had TSE working in quartus 13.1 (I built the system using Qsys). I havve updated to quartus 14 and now TSE no longer works. I get the following error:

    [altera_eth_tse_init] Error opening TX SGDMA

    init error -22 on net[0]

    Strangely enough, If I debug and step through the code, it will correctly find and initialize the TSE/PHY... but the program crashes soon after. The code that I am using hasn't changed from version 13 to version 14, I only updated the bsp. Any help would be greatly appreciated. FYI I am using the Arria V GX starter kit.

    --- Quote Start ---

    Hi,

    I have the same problem, my triple speed ethernet is ok with previous version of TSE + FreeRTOS and LWIP but with the update not, i have sgdma tx and rx. The sgdma RX seem to receive data, tx can send data, but there a stop in TSE (i suspect something with the PHY i use marvel rgmii 88E1111). the TSE User guide don't talk about a major update, and i can't found what's change...

    Can someone has already get a Triple speed ethernet since quartus 13.1 ?? maybe could we see a .qsys file and vhdl example ???

    thanks

    Simon

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    yazidneely,

    I did not resolve my problem because i have a specific design, but i open a support ticket and i got the folowing answer :

    --- Quote Start ---

    Hi Simon,

    Could you please ensure the following clock signal are connected correctly in your design?

    http://www.altera.com/support/kdb/solutions/rd02102014_389.html

    If this is still not working, please attach your design in this Service Request for us to further investigate.

    Have a nice day.

    Regards -SK

    --- Quote End ---

    I'm not a vhdl guru but i think that the new TSE got more signal than the older and you should edit your main vhdl or verilog file to connect them.

    Simon