Cyclone V Triple Speed Ethernet in Quartus 13.1

yazidneely,

I did not resolve my problem because i have a specific design, but i open a support ticket and i got the folowing answer :

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Hi Simon,

Could you please ensure the following clock signal are connected correctly in your design?

http://www.altera.com/support/kdb/solutions/rd02102014_389.html

If this is still not working, please attach your design in this Service Request for us to further investigate.

Have a nice day.

Regards -SK

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I'm not a vhdl guru but i think that the new TSE got more signal than the older and you should edit your main vhdl or verilog file to connect them.

Simon