Forum Discussion
Honored ContributorCyclone V speed is much slower
Hello. I am new to Cyclone V. I took my design for Cyclone III and recompiled it with Quartus II web 13.1. From the timing analyzer, I can see that the maximum clock rate is only 84 Mhz while I was getting 131 Mhz with cyclone III at the same C8N speed grade. The timing recommendation is incomprehensible. Would anyone who knows cyclone V well tell me if this is expected? Is Cyclone V significantly slower than Cyclone III? This doesn't make sense.
Thanks a lot. Jixiang34 Replies
Altera_ForumPost your TimeQuest report. It may be there are some cross clock domain paths that the tool is working hard on, then giving up on other paths.
Pete- Altera_Forum
Do note that Cyclone V using ALTERA_PLL ip instead of ALTPLL which is used for previous device family like Cyclone III and Cyclone IV.
Agree with nicejob comment, you may need to consider the speed grade of the device used. Do counter check the timing spec of Cyclone V device and compare to other previous series device timing spec in their I/O timing spreadsheet. https://www.altera.com/content/dam/altera-www/global/en_us/others/literature/hb/cyclone-v/cyclonev-io-timing.xls https://www.altera.com/content/dam/altera-www/global/en_US/others/literature/hb/cyclone-iv/cycloneiv_io_timing_qii10_0.xls - Altera_Forum
No, I don't have that warning any more.
- Altera_Forum
Just to clarify:
Do you still get the error "Critical Warning (332012): Synopsys Design Constraints File file not found: 'Flex01.sdc' ..." ? - Altera_Forum
from my understanding, newer device doesnt mean it is faster. You will have to look at the speed grade. Even if you choose a newer device but the slowest speed grade, it might still lose to an older device with the fastest speed grade.
- Altera_Forum
Could you post your project?
- Altera_Forum
Thanks to everyone who responded to my problems. I am trying everything to get this resolved. I am using Q 15.0, the latest. I have cleaned up my design but it didn't help. I added pipeline stages in my design but it didn't help.
In the timing report, the recommendation is the following Move 0 combinational nodes before the source and 3 after the destination for the path from corr|...3]~_Duplicate_54 to corr|..._1~mac_pl[0][16] [hide details] Issue: Unbalanced Combinational Logic From: shift_b[1][3]~_Duplicate_54 To: lpm_add_sub:adder_pipe[18]|add_sub_7ic:auto_generated|op_1~mac_pl[0][16] TimeQuest analysis: report timing Nodes to move after dest: 3 Nodes to move before source: 0 This message doesn't make sense to me. Can anyone help me to decipher this? Thanks in advance. - Altera_Forum
No sdc file would be a culprit. There's also other assignments for an entity that doesn't exist.
- Altera_Forum
Try using the current 15.0 version.
- Altera_Forum
The next question is why Altera allows compilation when there is no sdc file. If timing is not entered then such compilation is useless and should have been stpped with something like "very fatal and deadly error"
