Forum Discussion
Altera_Forum
Honored Contributor
10 years agoOk looking at the timing report, the paths in question are from CLK100 to RAMCLK.
Can you describe how these are related? Are they both 100 MHz from the the PLL? Anyway It appears the "Default" mode of the Altera_PLL is now Direct mode instead of source synchronous or zero delay buffer. This is probably the root of the issue. Page 3 of the PLL doc talks about this: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/altera_pll.pdf I would play with the Operation Mode on your PLL and I'm sure you will find a setting that will zero out that delay. Pete