Cyclone V speed is much slower

Hi Pete;

Thanks for the reply.

I have attached a zip file containing two timing reports. One report is from an older design using a Cyclone IV and version 11.1 software, the other is from a Cyclone V using 15.0 software. The older design passes timing without any problems and the newer design fails primarily due to the long clock delay. Both designs are very similar.

I'm no expert on Timequest, but as far as I can tell the clock delay reported is from the rising edge of the clock input pin to the internal clock arriving at the nodes. This input clock is multiplied up from 25MHz to 100MHz using a PLL. On the older design the PLL seems to be compensating the output from the PLL so that it occurs on the clock distribution tree with a very short delay relative to the input clock. On the newer design there's a fairly long delay between the input clock edge and the clock seen in the device. I have explored different settings in the PLL module, but so far have not been able to get it to compensate the clocks in a way that's similar to the older PLL module used on the Cyclone IV.

As you suggest, the actual difference between the clocks seen at various nodes within the FPGA seem to be small for both designs. My initial assumption was that since the clock delays were uniform throughout the design they shouldn't matter. Unfortunately, the longer clock delay is not playing well with my timing constraints and the result is that the fitter is adding undesirable delay elements on some of my input pins to compensate for these clock delays.

Thanks,

Steve