Cyclone V speed is much slower

sglow:

So is your problem from I/O to register or register to register?

The clock tree in the device should be balance so that all the I/O will have a similar clock insertion delay. So even if there is 4+ ns delay for the clock to register A, it should have a very similar delay for register B.

However the PLL will either compensate for IO delay or not. (I know the old default was to compensate for this but I'm wondering if this changed)

So if this is not compensated for IO timing can be difficult.

Can you attach a timing quest report?

Pete