Honored Contributor
Honored ContributorThanks. I have checked all warnings. Here is the messages. Sorry, it's long
Critical Warning (138069): Setting INCREMENTAL_COMPILATION to "OFF" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to "ON" instead. Warning (20013): Ignored assignments for entity "Flex01" -- entity does not exist in design Warning (20014): Assignment for entity set_instance_assignment -name CLOCK_SETTINGS Clock -to clock -entity Flex01 was ignored Warning (20014): Assignment for entity set_instance_assignment -name CLOCK_SETTINGS clockx2 -to clockx2 -entity Flex01 was ignored Warning (20028): Parallel compilation is not licensed and has been disabled Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity dcfifo_gkl1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_d09:dffpipe16|dffe17a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_c09:dffpipe12|dffe13a* Critical Warning (332012): Synopsys Design Constraints File file not found: 'Flex01.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" Info (332110): Deriving PLL clocks Info (332110): create_clock -period 20.833 -waveform {0.000 10.416} -name PLL1IN PLL1IN Info (332110): create_generated_clock -source {myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 8 -multiply_by 125 -duty_cycle 50.00 -name {myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} Info (332110): create_generated_clock -source {myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 6 -duty_cycle 50.00 -name {myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[0] to: clkout Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -3.839 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -3.839 -1940.855 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): -0.629 -0.629 PLL1IN Info (332146): Worst-case hold slack is -1.915 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.915 -1.915 PLL1IN Info (332119): 0.247 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 0.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.666 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 2.381 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 9.090 0.000 PLL1IN Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[0] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -4.424 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -4.424 -2522.605 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): -0.532 -0.532 PLL1IN Info (332146): Worst-case hold slack is -1.981 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.981 -1.981 PLL1IN Info (332119): 0.159 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 0.666 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.666 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] Info (332119): 2.323 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk Info (332119): 8.993 0.000 PLL1IN Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[0] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 0.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.000 0.000 PLL1IN Info (332119): 2.113 0.000
