Forum Discussion

JWies1's avatar
JWies1
Icon for New Contributor rankNew Contributor
7 years ago

Cyclone V SoC: When routing HPS CAN0 or CAN1 pins to FPGA receive direction isn't working

I'm using Quartus Prime Lite 16.1. I am programming a Cyclone V Soc on a SocKit / DeNano board. I am accessing the CAN controllers with bare metal code from the second ARM core. With Qsys I select...
JWies1's avatar
JWies1
Icon for New Contributor rankNew Contributor
7 years ago

Hello!

1

CAN is NOT enabled in device tree because I'm NOT using Linux

2

I will signal TAP, but I guess that will only tell me what I already know:

transmit is working, receive signal is correct in FPGA but does not reach HPS.

3

There is a Linux working on core 0, but it has no CAN driver and no CAN in device tree.

CAN is accessed by core 1 with bare metal software, only.

Joachim