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New Contributor

5 years ago

Cyclone V SoC F2SDRAM Read Interface Ready cmd_ready_0 Not Asserting

Hello, I am trying to develop a simple design with an Altera DMA Controlelr Core IP (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2cpu_nii51006.pdf) that reads f...

EBERLAZARE_I_Intel

Regular Contributor

5 years ago

Hi,

Can you check if you have set the correct base addresses of the slaves in your design that is connected to the HPS AXI master bridge?:

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

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Cyclone V SoC F2SDRAM Read Interface Ready cmd_ready_0 Not Asserting

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