Cyclone V SoC Development Kit

Question

Hi guys,

I have bought this kit recently and ran some provided reference design examples on it (Altera Quartus projects, DS-5, RocketBoards.org, and so on). They work great.

Now, I want to learn more about this device and/or its provided IPs (in Qsys). I also want to learn more about its capability (i.e. what daughter cards or extension boards can interface with it). So, can I ask you, or at least, do you know what other modules or boards I should consider buying in order to interface with my board ?? Where should I look into ??

Thanks,

th_altera

altera_forum · Answer

Hi,

I would suggest you take a look on Design Store (https://cloud.altera.com/devstore/platform/?acds_version=any&board=22) and also Rocketboards (https://rocketboards.org/foswiki/documentation/alterasocdevelopmentboard) to check out more =)

altera_forum · Answer

Altera's website contains a list of daughter cards and their supported devices:

https://www.altera.com/products/boards_and_kits/daughter-cards.html

Most importantly though - you should decide what is your desired interface, and then look for the suitable add-on cards that fulfill the need. Some of the add-on cards can be very expensive

altera_forum · Answer

Hi Aaron, Thanks for your reply. I appreciated that. I have bookmarked the store site and will look for more examples there. Have a nice day, TH

altera_forum · Answer

Hi sunshine,

I have looked at the terasic site recently. I will have to decide what daughter cards and/or what interfaces i should check out next.

And yes, cost is my biggest decision maker (or breaker) here.

Thanks,

Have a nice day,

TH

altera_forum · Answer

Hi guys,

Can I ask if you know whether the ARRADIO evaluation board is compatible with the Cyclone V SoC Development Kit or not ??

The wiki page is provided below:

https://wiki.analog.com/resources/eval/user-guides/arradio

Thanks,

Have a nice day,

TH

Forum Discussion

Cyclone V SoC Development Kit

5 Replies

Recent Discussions

Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information