Cyclone V SOC: access HPS CAN controller from NIOS in FPGA

I found a solution. I don't have time to explain fully. The key is setting the appropriate bit(s) in the l4sp register (part of the l3regs group) that allow the f2h_axi_bridge access to the desired HPS device(s), such as CAN0. I cannot see any way to have Platform Designer/Quartus set the l4sp register as part preloader or FPGA image. The ARM processor has to do it (in Linux open /dev/mem and use mmap() to write the register).