Cyclone V SoC - Shared Memory Controller

Hi kstolp,

I did not use the address expander. I prefer to access the Avalon-MM bus directly since I am not connecting to a NIOS on the FPGA but only to my own FPGA logic which can address the memory with no issues. I've found the avalon interface to be pretty user friendly so it didn't take long to write some VHDL to access the port.

I have not had to explicitly take any of the bridges out of reset, although I believe the way to do this is to write directly to the "rstmgr > brgmodrst" registers at 0xFFD0501C (see http://www.altera.com/literature/hb/cyclone-v/hps.html)

I know that the pre-loader does something differently after you enable the F2H SDRAM port since it changes some of the generated software files are changed (e.g. hps.xml <config name='F2SDRAM_READ_PORT_USED' value='1' />). If you don't update the pre-loader then the avalon-MM interface to your F2H SDRAM port will hold "waitrequest" high and so you can't request any reads or writes (maybe because the bridge was in reset?).

I think that the pre-loader must be taking the bridges out of reset since I am not doing this in my application code?