Cyclone V SoC - Shared Memory Controller

Dave,

Thanks for the feedback. I will try your lessons learned in my design. The 0x2000_0000 offset you add is interesting. It would be nice to know why, but for now, I'll give it a try. I assume you are using the address span extender to interface your fpga masters to the F2H SDRAM port (as BadOmen has pointed out). Is this correct?

I was already doing your preloader delete the directory trick. One thing that has not been obvious to me is where the F2H SDRAM port is configured in the software chain. You have indicated that this does get taken care of by the preloader generated by the bsp-editor. Other than the preloader trick, is there anything else that needs to be done to configure the F2H SDRAM port? BadOmen has stated that the bridges need to be taken out of reset. I have not come across such a requirement for the F2H SDRAM port. Is this your understanding as well?

Thanks again,

-kstolp