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Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Also I forgot to add that you need to make sure you re-generate the preloader when you change your HPS to have the F2H SDRAM port in QSYS. I had to delete the entire spl-bsp directory before generating the pre-loader since there is a bug which means it doesn't update some files if they already exist.

If the preloader doesn't know about the F2H SDRAM port it will not be correctly configured and when you attempt to read it crashes (I also experienced this).