Cyclone V SoC - Shared Memory Controller

Taz1984,

Were you able to resolve your issue with DS-5? I have been trying to access the hps sdram from the fpga side using the f2h_sdram interfaces with no success. I'm not sure why, but if I try to access SDRAM from the FPGA side, the DS-5 debugger looses communications with the MPU. This indicates to me that accessing the SDRAM from the FPGA side is locking up the SDRAM controller and crashing the MPU. I'm trying to understand what has to be done in the SDRAM controller to properly configure the f2h_sdram interfaces, and whether this should happen in the preloader or the u-boot process?

I appreciate any insight anyone may have on this issue.

Thanks

-kstolp