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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

That sounds like the bridge hasn't been opened up. For a master in the HPS (like the CPU) to be able to access anything in the FPGA the following is required:

1 - Bridge needs to be clocked and pulled out of reset

2 - Bridge needs to be enabled in the address map (this is enabled in the GPV of the L3 interconnect)

By default the HPS-to-FPGA bridges are not mapped in after the system comes out of reset so software has to do that.